Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process.

Area of Science:

• • Integrated circuit design
• • Gallium Arsenide (GaAs) Heterojunction Bipolar Transistor (HBT) technology

Background:

• • Phase-locked loops (PLLs) are critical for frequency synthesis in modern electronics.
• • Existing PLL designs face challenges in achieving wide bandwidth, low noise, and high frequency operation simultaneously.

Purpose of the Study:

• • To design and implement a novel charge pump phase-locked loop (CPPLL) frequency source.
• • To improve the performance of key PLL components, including the frequency discriminator and charge pump.

Main Methods:

• • Fabrication of a CPPLL circuit using a 0.15 μm Win GaAs pHEMT process.
• • Design of an improved fully differential edge-triggered frequency discriminator (PFD).
• • Development of an improved differential structure charge pump (CP).
• • Integration of a low-noise voltage-controlled oscillator (VCO) and a static 64:1 frequency divider.

Main Results:

• • Achieved an output signal frequency range of 3.584 GHz to 4.021 GHz.
• • Demonstrated a phase noise of -117.82 dBc/Hz at a 1 MHz offset.
• • Measured maximum output power of 4.34 dBm with a chip area of 2701 μm × 3381 μm and power consumption of 181 mW.

Conclusions:

• • The proposed CPPLL circuit effectively integrates improved PFD and CP modules with a low-noise VCO and frequency divider.
• • The design achieves competitive performance metrics, including frequency range, phase noise, and output power.
• • The 0.15 μm Win GaAs pHEMT process is suitable for realizing high-performance frequency source circuits.