Design of FPGA-Based SHE and SPWM Digital Switching Controllers for 21-Level Cascaded H-Bridge Multilevel Inverter...

Area of Science:

• Power Electronics
• Digital Control Systems
• Embedded Systems

Background:

• Multilevel inverters are crucial for high-voltage/high-power applications, converting DC to AC.
• Existing Field-Programmable Gate Array (FPGA)-based controllers face limitations in memory usage and architectural complexity.
• Microcontrollers and Digital Signal Processors (DSPs) have drawbacks like limited sampling rates and execution speeds.

Purpose of the Study:

• To propose two novel FPGA-based digital switching controllers: Selective Harmonic Elimination (SHE) and Sinusoidal Pulse Width Modulation (SPWM).
• To design controllers with minimal hardware complexity and logic utilization for a 21-level multilevel inverter.
• To verify the real-time performance and efficiency of the proposed controllers.

Main Methods:

• Developed SHE and SPWM controllers using Verilog Hardware Description Language (HDL).
• Verified functionality using testbenches and synthesized designs for an Intel FPGA (DE2-115) board.
• Performed system-level verification via HDL co-simulation in MATLAB Simulink for a 21-level cascaded H-Bridge inverter.

Main Results:

• The SHE and SPWM controllers utilized minimal logic resources (186 and 369 Logic Elements, respectively), less than 1% of the FPGA capacity.
• The SHE controller demonstrated a 99.97% faster execution speed compared to a microcontroller (PIC16F877A).
• The SHE controller achieved a lower Total Harmonic Distortion (THD) of 3.91% (37% less than SPWM's 6.17%).

Conclusions:

• The proposed simplified SHE and SPWM controllers require minimal logic resources and achieve high processing speeds.
• Controllers function correctly on real-time FPGA hardware and generate a 21-level stepped sine-wave output voltage (±360 V_PP) at 50 Hz.
• The SHE controller provides superior performance with significantly lower THD compared to the SPWM controller.