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Engineering Top Gate Stack for Wafer-Scale Integrated Circuit Fabrication Based on Two-Dimensional Semiconductors.

Jingyi Ma1, Xinyu Chen1, Xinyu Wang1

  • 1State Key Laboratory of ASIC and System, School of Microelectronics, Zhangjiang Fudan International Innovation Center, Fudan University, Shanghai 200433, China.

ACS Applied Materials & Interfaces
|February 25, 2022
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A novel non-destructive doping method precisely controls the threshold voltage of molybdenum disulfide field-effect transistors (MoS2-FETs) on a wafer scale. This technique enables the fabrication of integrated logic circuits from 2D semiconductors.

Area of Science:

  • Materials Science
  • Nanotechnology
  • Electrical Engineering

Background:

  • Two-dimensional (2D) semiconductors are gaining traction for advanced electronic devices.
  • Transitioning from basic field-effect transistors (FETs) to complex circuits faces integration challenges.
  • Precise control over device characteristics like threshold voltage is crucial for circuit design.

Purpose of the Study:

  • To develop a non-destructive, wafer-scale doping strategy for MoS2-FETs.
  • To precisely modulate the threshold voltage (VTH) of MoS2-FETs.
  • To demonstrate the application of this doping strategy in fabricating functional logic circuits.

Main Methods:

  • A non-destructive doping approach using a variable-thickness aluminum (Al) interlayer between the high-k dielectric and gold top gate (TG).
Keywords:
Al interlayerdipole effectlogic circuittop gatetwo-dimensional material

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  • Controlled oxidation of the Al interlayer to create oxygen vacancies (Vo) in the high-k dielectric, inducing stable electron doping.
  • Wafer-scale fabrication and characterization of MoS2-FETs with modulated VTH.

    • Main Results:

    • Achieved precise, wafer-scale modulation of MoS2-FET threshold voltage (VTH).
    • Successfully optimized an inverter circuit by matching driver and load transistors.
    • Fabricated digital logic blocks demonstrating desired logic functions.

    Conclusions:

    • The proposed Al interlayer strategy offers a scalable and non-destructive method for doping 2D semiconductors.
    • This technique facilitates the integration of MoS2-FETs into complex, functional logic circuits.
    • The approach shows significant potential for fabricating fully integrated, multistage logic circuits using wafer-scale 2D materials.