On-Chip Structures for F Binning and Optimization.

Area of Science:

• Electrical Engineering
• Computer Engineering
• Semiconductor Manufacturing

Background:

• Manufacturing process variations cause chip performance differences, necessitating maximum operation frequency (Fmax) testing for speed binning.
• Current Fmax testing aims to reduce cost and improve binning accuracy, but conservative binning limits profit potential.

Purpose of the Study:

• To present a novel adaptive methodology for speed binning to increase overall profit by promoting chips to higher speed bins.
• To optimize the Fmax yield of digital circuits with redundant timing in the clock tree.

Main Methods:

• Identification and adaptation of critical speed paths using an on-chip Binning Checker and Binning Adaptor.
• Integration of the adaptive methodology into existing Fmax tests with minimal extra cost.

Main Results:

• The number of higher bin chips improved by 7-16% across five benchmarks on 28 nm Altera FPGAs.
• Cost analysis indicated a profit increase ranging from 1.18% to 3.04%.

Conclusions:

• The proposed adaptive speed binning methodology effectively increases chip profit by promoting marginal chips to higher bins.
• The system is validated on multiple benchmarks and offers a low-cost solution for optimizing Fmax yield.