Vertical MoS₂ transistors with sub-1-nm gate lengths.

Area of Science:

• Materials Science
• Nanotechnology
• Solid State Physics

Background:

• Ultra-scaled transistors are crucial for next-generation electronics.
• Fabricating transistors with gate lengths below 1 nanometer using atomically thin materials like molybdenum disulfide (MoS2) remains a significant challenge.

Purpose of the Study:

• To demonstrate side-wall MoS2 transistors with sub-1 nm gate lengths.
• To utilize the edge of graphene as a gate electrode for ultra-scaled transistors.

Main Methods:

• Fabrication of side-wall MoS2 transistors using large-area graphene and MoS2 films grown by chemical vapor deposition.
• Integration of these materials on a 2-inch wafer for scalable device production.

Main Results:

• Demonstrated side-wall MoS2 transistors with an atomically thin channel and physical gate length below 1 nm.
• Achieved high On/Off ratios (up to 1.02 × 10^5) and low subthreshold swing (down to 117 mV dec^-1).
• Simulations showed effective channel lengths approaching 0.34 nm (On state) and 4.54 nm (Off state).

Conclusions:

• This novel approach enables the creation of ultra-scaled transistors crucial for future electronic devices.
• The demonstrated technology can significantly contribute to the continued scaling of transistors, potentially extending Moore's Law.