Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders.

Area of Science:

• Electrical Engineering
• Telecommunications Engineering
• Computer Engineering

Background:

• 5th-generation (5G) New Radio (NR) systems rely on Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders for error correction.
• Existing QC-LDPC decoder architectures face challenges in hardware complexity and supporting diverse submatrix sizes.

Purpose of the Study:

• To propose a novel Multi-Size Cyclic Shift Network (MCSN) structure for 5G NR QC-LDPC decoders.
• To reduce the hardware complexity of QC-LDPC decoders while maintaining performance.
• To support all 51 submatrix sizes defined in the 5G NR standard efficiently.

Main Methods:

• A fine-coarse approach is used to decompose cyclic shift sizes.
• The MCSN structure comprises a pre-rotator for fine shifts and a main rotator for coarse shifts.
• A Forward Routing Circular-Shift (FRCS) network based on barrel shifters is employed.

Main Results:

• The proposed MCSN structure achieves a substantial reduction in hardware complexity.
• The design supports all 51 submatrix sizes specified in the 5G NR standard.
• Experimental results show up to 56.75% area saving on TSMC 65-nm CMOS technology compared to prior works.

Conclusions:

• The MCSN structure offers a highly efficient and hardware-complexity-reduced solution for 5G NR QC-LDPC decoders.
• The cyclic shift size decomposition method effectively minimizes hardware resources.
• This work provides a significant advancement for 5G communication system hardware design.