Multi-Unit Serial Polynomial Multiplier to Accelerate NTRU-Based Cryptographic Schemes in IoT Embedded Systems

Area of Science:

• Cryptography and Security Engineering
• Embedded Systems Design
• Post-Quantum Cryptography

Background:

• Internet of Things (IoT) devices require robust security for data integrity, privacy, and authenticity.
• Quantum computing advancements necessitate new cryptographic approaches for embedded systems.
• Lattice-based cryptography offers efficient solutions for resource-constrained IoT environments.

Purpose of the Study:

• To describe the hardware implementation of polynomial multipliers for NTRU cryptographic schemes.
• To enhance the performance of time-consuming operations in embedded cryptographic applications.
• To provide flexible and secure cryptographic primitives for evolving IoT security needs.

Main Methods:

• Hardware implementation of parameterized multi-unit serial polynomial multipliers.
• Integration of designs as AXI4 bus-compliant intellectual property modules.
• Characterization and performance evaluation on Xilinx Zynq-7000 and Zynq UltraScale+ devices.

Main Results:

• Achieved acceleration factors of up to 3.1 compared to software implementations.
• Demonstrated plug-and-play inclusion as hardware accelerators in the LibNTRU library.
• Provided extensive implementation and characterization results for NTRUEncrypt standard parameters.

Conclusions:

• The developed hardware multipliers significantly speed up NTRU-based cryptography in embedded systems.
• The flexible design allows adaptation to standardized and emerging post-quantum cryptographic proposals.
• The solution offers a favorable cost/performance/security trade-off for IoT applications.