Fully integrated parity-time-symmetric electronics

Area of Science:

• Integrated Circuit Design
• Non-Hermitian Physics
• Microwave Engineering

Background:

• Parity-time (PT) symmetry with balanced gain and loss offers opportunities in electronics, including wireless energy transfer and topological defect engineering.
• Current PT symmetry implementations often use ad hoc methods, operate at low frequencies, and lack large-scale integration capabilities.

Purpose of the Study:

• To demonstrate a fully integrated realization of parity-time symmetry in a standard complementary metal-oxide-semiconductor (CMOS) process technology.
• To showcase PT symmetry features like phase transitions and manipulation of broadband microwave generation and propagation.

Main Methods:

• Development of a novel integrated circuit design implementing parity-time symmetry within a standard CMOS process.
• Experimental validation of PT symmetry features, including phase transitions and broadband microwave manipulation.

Main Results:

• Achieved a 2.1 times increase in bandwidth and a 30% noise reduction in microwave generation compared to conventional methods.
• Demonstrated large non-reciprocal microwave transport from 2.75 to 3.10 GHz in the non-oscillatory mode, attributed to enhanced nonlinearities.
• Successfully exhibited salient PT symmetry features, such as phase transitions, in the integrated system.

Conclusions:

• The fully integrated PT symmetry system in CMOS technology overcomes limitations of existing schemes in terms of operating frequency and integration scale.
• This approach enriches integrated circuit design, enabling exploration of topological effects in high-dimensional non-Hermitian systems using scalable technology.