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Correction: Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray
Dmitry Dzhigaev1, Johannes Svensson2, Abinaya Krishnaraja2
1Division of Synchrotron Radiation Research and NanoLund, Department of Physics, Lund University, P.O. Box 118, SE-221 00 Lund, Sweden. dmitry.dzhigaev@sljus.lu.se.
Nanoscale
|March 23, 2022
Summary
This correction clarifies strain mapping in vertical nanowire transistors. Advanced scanning X-ray nanodiffraction techniques were used to analyze these crucial semiconductor devices.
Area of Science:
- Materials Science
- Condensed Matter Physics
- Nanotechnology
Context:
- Vertical nanowire transistors are critical components in modern electronics.
- Accurate strain characterization is essential for optimizing device performance and reliability.
- Previous studies may have had limitations in precisely mapping strain within individual nanowires.
Purpose:
- To provide a correction to a previously published paper on strain mapping in vertical nanowire transistors.
- To ensure the accuracy of strain distribution data obtained through scanning X-ray nanodiffraction.
- To refine the understanding of mechanical stress effects on nanowire device functionality.
Summary:
- This work corrects specific details concerning the strain mapping analysis of a processed vertical nanowire transistor.
- The correction pertains to data obtained using scanning X-ray nanodiffraction, a high-resolution technique.
- It ensures the fidelity of the reported strain profiles within the individual nanowire device.
Impact:
- Improved accuracy in understanding strain effects in nanoscale electronic devices.
- Enhanced reliability of future research relying on strain mapping data in nanowire transistors.
- Contributes to the precise engineering of next-generation semiconductor technologies.

