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Dielectric Walls/Layers Modulated 3D Periodically Structured SERS Chips: Design, Batch Fabrication, and Applications.
Yi Tian1, Haifeng Hu1, Peipei Chen1,2
1Nanofabrication Laboratory, CAS Key Laboratory for Nanophotonic Materials and Devices, CAS Key Laboratory for Nanosystems and Hierarchical Fabrication, CAS Center for Excellence in Nanoscience, National Center for Nanoscience and Technology, Beijing, 100190, China.
Dielectric structures significantly boost surface-enhanced Raman scattering (SERS) performance in plasmonic materials. Optimized dielectric walls enhance localized surface plasmon resonance, leading to a 265-fold increase in SERS chip efficiency for detecting trace mercury ions.
Area of Science:
- Materials Science
- Nanotechnology
- Spectroscopy
Background:
- Dielectrics are crucial for surface-enhanced Raman scattering (SERS) by influencing surface plasmon excitation and propagation.
- The precise role of dielectric structures in 3D plasmonic systems for SERS remains less understood compared to plasmonic materials themselves.
Purpose of the Study:
- To investigate the impact of vertical dielectric walls and layers in 3D plasmonic structures on SERS.
- To optimize dielectric configurations for maximizing surface plasmon polariton (SPP) interference and localized surface plasmon resonance (LSPR).
- To develop a high-performance, cost-effective SERS chip for trace analyte detection.
Main Methods:
- Fabrication of 3D periodic plasmonic/dielectric structures using nanoimprint lithography.
- Simulation and experimental analysis of SPP interference within dielectric walls of varying thicknesses.
- Characterization of SERS enhancement factors for designed gold/silica (Au/SiO2) structures.
Main Results:
- Maximizing SPP interference within dielectric walls at specific thicknesses (integral multiples of half-SPP wavelength) significantly enhances LSPR and SERS.
- Designed Au/SiO2 SERS chips achieved an enhancement factor of 8.9 × 10^10, 265 times higher than controls with thinner walls.
- Batch fabrication of 1200 SERS chips on a 4-inch wafer was demonstrated.
Conclusions:
- Vertical dielectric walls in 3D plasmonic structures are highly effective in enhancing SERS performance.
- The developed platform enables low-cost, large-scale fabrication of high-performance SERS chips.
- The Au/SiO2 SERS chips successfully detected mercury ions at concentrations as low as 1 part per trillion (ppt).
