Power and Area Efficient Cascaded Effectless GDI Approximate Adder for Accelerating Multimedia Applications Using...

Area of Science:

• Computer Engineering
• VLSI Design
• Approximate Computing

Background:

• Approximate computing accelerates error-tolerant applications like deep learning by reducing computational effort.
• The dark silicon era necessitates low-power alternatives to Complementary Metal Oxide Semiconductor (CMOS) technology.
• Gate Diffusion Input (GDI) logic offers reduced transistor count and lower power consumption compared to CMOS.

Purpose of the Study:

• To propose a novel, energy and area-efficient 1-bit GDI-based full adder (EAFA) with minimal error distance.
• To mitigate the cascaded effect problem inherent in GDI-based circuits.
• To extend the 1-bit adder into 16-bit Energy and Area Efficient High-Speed Error-Tolerant Adders (EAHSETA).

Main Methods:

• Designed a novel 1-bit GDI-based full adder (EAFA) architecture.
• Extended the EAFA to create segmented 16-bit EAHSETA circuits.
• Simulated design metrics (delay, area, power) using Cadence tool.
• Deployed the EAHSETA for accelerating convolution in a neural network for handwritten digit classification on an Intel Cyclone IV FPGA.

Main Results:

• The proposed EAHSETA demonstrated reduced logic element usage and improved operational speed.
• Achieved a speed-up factor of 1.29 compared to similar techniques.
• Real-time handwritten digit classification achieved 95% accuracy.

Conclusions:

• The proposed GDI-based adder architecture is energy and area efficient for high-speed, error-tolerant applications.
• This approach effectively accelerates deep learning processes, such as neural network convolution, on FPGAs.
• Offers a promising alternative to CMOS for low-power, high-performance computing in portable devices.