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Related Experiment Video

Updated: Sep 26, 2025

Microfluidic Imaging Flow Cytometry by Asymmetric-detection Time-stretch Optical Microscopy ATOM
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Resources and Power Efficient FPGA Accelerators for Real-Time Image Classification.

Angelos Kyriakos1, Elissaios-Alexios Papatheofanous1, Charalampos Bezaitis1

  • 1Electronics Laboratory, Faculty of Physics, National and Kapodistrian University of Athens, 15772 Athens, Greece.

Journal of Imaging
|April 21, 2022
PubMed
Summary
This summary is machine-generated.

This study presents a Field-Programmable Gate Array (FPGA) accelerator for Convolutional Neural Networks (CNNs) designed for efficient image processing on edge devices. The hardware accelerator optimizes performance and power consumption for real-time object detection tasks.

Keywords:
CNNFPGAacceleratorimage processingvessel detection

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Area of Science:

  • Computer Engineering
  • Artificial Intelligence
  • Embedded Systems

Background:

  • Real-time image and video processing demands hardware acceleration for complex tasks like object detection using Machine Learning (ML) and Convolutional Neural Networks (CNNs).
  • Existing solutions often require significant resources, limiting their application in resource-constrained environments such as edge, mobile, and satellite computing.

Purpose of the Study:

  • To design and implement a Field-Programmable Gate Array (FPGA) accelerator for CNNs with a limited feature space.
  • To improve performance, reduce power consumption, and optimize resource utilization for image processing applications on single FPGA devices.

Main Methods:

  • The study proposes a design approach targeting efficient utilization of logic and memory resources on a single FPGA.
  • An FPGA accelerator was developed for vessel detection using a Xilinx Virtex 7 XC7VX485T FPGA.
  • The architecture processes RGB images (80x80) or sliding windows and was trained on the 'Ships in Satellite Imagery' dataset.

Main Results:

  • The developed FPGA accelerator achieved a frequency of 270 MHz.
  • Inference was completed in 0.687 ms.
  • The system demonstrated a power consumption of 5 watts.

Conclusions:

  • The proposed FPGA design approach effectively accelerates CNNs for image processing tasks, particularly for applications in edge, mobile, and satellite computing.
  • The validated accelerator demonstrates significant improvements in performance and power efficiency for real-time object detection.