FPGA Correlator for Applications in Embedded Smart Devices.

Area of Science:

• Digital Signal Processing
• Hardware Acceleration
• Embedded Systems Engineering

Background:

• Software-based correlators are computationally intensive, limiting real-time analysis on embedded devices.
• Field Programmable Gate Arrays (FPGAs) offer a solution for high-performance computing in resource-constrained environments.

Purpose of the Study:

• To present a detailed register-level FPGA-based correlator design.
• To provide open-source Very High-Speed Integrated Circuit Hardware Description Language (VHDL) code for linear and multi-tau correlators.
• To validate the performance and accuracy of the FPGA correlator design.

Main Methods:

• Developed a register-level FPGA correlator design with unified data interfaces.
• Implemented base modules for linear and multi-tau correlators.
• Validated the design using constant, pulse, and sine signal datasets against software correlators and theoretical values.

Main Results:

• The FPGA correlators achieved identical accuracy to software counterparts across all tested datasets.
• Achieved a computation speed at least 85,000 times faster than software correlators on a Xilinx MicroBlaze processor.
• Demonstrated the feasibility of integrating FPGA correlators into System on a Chip (SoC) solutions.

Conclusions:

• FPGA-based correlators provide a viable and highly efficient hardware acceleration for signal processing.
• The presented design is suitable for embedded devices and System on a Chip (SoC) applications, particularly in biosensing.
• The open-source VHDL code facilitates easy implementation and integration of high-performance correlation capabilities.