An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy

Area of Science:

• Cryptography and Information Security
• Hardware Implementation of Algorithms
• Fault-Tolerant Computing

Background:

• Cryptographic hash functions like SHA-3 are essential for security in IoT, IIoT, Industry 4.0, and automotive applications.
• Hardware implementations on FPGAs are vulnerable to errors from noise and radiation, impacting data integrity.
• Existing solutions primarily focus on error detection, lacking robust error correction for SHA-3.

Purpose of the Study:

• To design and analyze novel FPGA architectures for SHA-3 with integrated fault tolerance.
• To implement error detection and correction mechanisms for SHA-3 hardware.
• To compare the performance of fault-tolerant SHA-3 architectures against non-fault-tolerant designs and existing literature.

Main Methods:

• Developed four FPGA architectures for SHA-3: two without fault tolerance and two with fault tolerance.
• Integrated Hamming Codes with Encoder and Decoder modules at the step-mapping functions level for error handling.
• Conducted comparative analysis based on experimental results including frequency, resource utilization, throughput, and efficiency.

Main Results:

• Fault-tolerant architectures demonstrated the capability to detect up to 120 and 240 errors per KECCAK-p run in worst-case scenarios.
• The proposed designs offer a significant advancement over existing error detection-only methods.
• Comparative analysis highlighted the trade-offs in performance metrics for the fault-tolerant designs.

Conclusions:

• The presented fault-tolerant SHA-3 hardware architectures effectively detect and correct errors, crucial for reliable operation in harsh environments.
• These solutions address a critical gap in securing SHA-3 implementations against hardware faults.
• The findings provide valuable insights for developing robust cryptographic hardware for next-generation technologies.