A 78.8-84 GHz Phase Locked Loop Synthesizer for a W-Band Frequency-Hopping FMCW Radar Transceiver in 65 nm CMOS

Area of Science:

• Electrical Engineering
• Microwave Engineering
• Integrated Circuit Design

Background:

• Frequency hopping frequency modulation continuous wave (FMCW) radar requires agile frequency synthesizers.
• Traditional phase-locked loops (PLLs) can introduce overhead for rapid frequency hopping.

Purpose of the Study:

• To implement a W-band integer-N PLL for frequency hopping FMCW radar.
• To achieve high performance and efficient frequency hopping using a novel VCO architecture.

Main Methods:

• Designed a cross-coupled voltage-controlled oscillator (VCO) with a push-pull buffer in 65-nm CMOS technology.
• Utilized gate voltage control of the buffer to modify VCO load susceptance for frequency hopping.
• Integrated the VCO with a third-order loop filter and a divider chain (modulus 48) to form the PLL.

Main Results:

• The stand-alone VCO achieved 13.5 dBm output power, 9.6% peak efficiency, and 3.5% tuning range.
• VCO phase noise was -92.6 dBc/Hz at 1-MHz and -106.1 dBc/Hz at 10-MHz offset.
• The implemented PLL demonstrated a locking range from 78.84 GHz to 84 GHz with -85.2 dBc/Hz phase noise at 1-MHz offset.

Conclusions:

• The proposed W-band PLL architecture effectively enables frequency hopping for FMCW radar with minimal implementation overhead.
• The integrated circuit achieves competitive performance metrics for high-frequency radar applications.
• This design offers a viable solution for next-generation radar systems requiring agile frequency agility.