Optimizing the Deep Neural Networks by Layer-Wise Refined Pruning and the Acceleration on FPGA.

Area of Science:

• Artificial Intelligence
• Computer Engineering
• Deep Learning

Background:

• Deep neural networks (DNNs) are computationally intensive, limiting their practical application.
• Accelerating DNN inference is crucial for real-time AI systems.
• Existing pruning methods may require additional training or introduce overhead.

Purpose of the Study:

• To propose a high-efficiency layer-wise refined pruning method for DNNs at the software level.
• To accelerate DNN inference at the hardware level using field-programmable gate arrays (FPGAs).
• To demonstrate the method's effectiveness and applicability to various DNN architectures.

Main Methods:

• A layer-wise refined pruning method based on channel-wise importance and input sparsity.
• Software-level pruning integrated with native network characteristics, avoiding extra training workloads.
• Hardware-level acceleration on FPGA using the Vitis AI tool.

Main Results:

• Significant pruning of parameters and Floating-Point Operations (FPO) achieved: over 85% for ResNet50/101 and 75.78% for VGG13BN, with minimal accuracy loss (<0.74%).
• Achieved high throughput on FPGA: 151.99 fps for VGG13BN and 124.31 fps for ResNet101 (two threads mode).
• Demonstrated speedups of up to 4.3x for VGG13BN and 1.8x for ResNet101 on FPGA compared to original networks.

Conclusions:

• The proposed pruning method effectively reduces DNN complexity with negligible accuracy degradation.
• Hardware acceleration on FPGAs significantly boosts inference speed for pruned DNNs.
• This approach offers a practical solution for deploying efficient DNNs in real-world applications.