Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In...

Area of Science:

• Electrical Engineering
• Computer Engineering
• Materials Science

Background:

• Large-scale memories in System-on-Chips (SOCs) present repair challenges due to poor accessibility.
• Conventional external testing methods are insufficient for repairing embedded memories.
• Redundancy techniques, replacing faulty rows/columns with spares, are crucial for improving memory yield.

Purpose of the Study:

• To propose a novel fault detection and Built-In Self-Repair (BISR) method for Static Random Access Memory (SRAM).
• To enhance the fault tolerance and yield of embedded memories in SOCs.
• To reduce the maximum operating frequency and total power consumption of memory systems.

Main Methods:

• Deep Q-learning (DQL) integrated with Bit-Swapping-based linear feedback shift register (BSLFSR) for Fault Detection (DQL-BSLFSR-FD).
• Memory Built-In Self-Test (MBIST) utilizing DQL for fault injection and test pattern control.
• BSLFSR-based Built-In Self-Repair (BISR) model for redundancy analysis and replacement of faulty cells with spares.

Main Results:

• The DQL-BSLFSR-FD model achieved a reduction of 23.5% and 29.5% in maximum operating frequency (minimum clock period).
• Total power consumption was reduced by 34.9% and 26.7% compared to existing approaches.
• The method was designed, implemented on FPGA, and simulated using Verilog.

Conclusions:

• The proposed DQL-BSLFSR-FD method offers a highly effective solution for fault detection and repair in SRAM.
• This approach significantly improves memory yield and reduces power consumption and operating frequency.
• The successful FPGA implementation and simulation validate the efficacy of the proposed memory BIST and BISR techniques.