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A Timing-Based Split-Path Sensing Circuit for STT-MRAM.
Bayartulga Ishdorj1, Jeongyeon Kim1, Jae Hwan Kim1
1Department of Electronics Engineering, Incheon National University, Incheon 22012, Korea.
Micromachines
|July 27, 2022
Summary
Spin-transfer torque magnetoresistive random access memory (STT-MRAM) requires advanced sensing circuits for reliable operation. A novel timing-based split-path sensing circuit (TSSC) significantly improves read yield by minimizing voltage mismatch effects.
Area of Science:
- Semiconductor device physics
- Integrated circuit design
- Non-volatile memory technologies
Background:
- Spin-transfer torque magnetoresistive random access memory (STT-MRAM) offers a compelling alternative for universal memory due to its cost and performance advantages.
- Scaling challenges and decreasing supply voltages in deep submicron technologies necessitate advanced sensing circuits (SC) for reliable STT-MRAM operation.
- Conventional split-path sensing circuits (SPSC) face limitations in read yield due to process fluctuations and threshold voltage mismatches.
Purpose of the Study:
- To propose a novel timing-based split-path sensing circuit (TSSC) for STT-MRAM applications.
- To enhance the read yield of STT-MRAMs in advanced technology nodes.
- To address the limitations of conventional sensing circuits in mitigating threshold voltage mismatch effects.
Main Methods:
- Development of a timing-based dynamic reference voltage technique within the split-path sensing circuit architecture.
- Implementation and simulation of the proposed TSSC using industry-compatible 28-nm model parameters.
- Comparative analysis of TSSC against conventional SPSC under nominal supply voltage (VDD = 1.0 V) considering iso-area and iso-power constraints.
Main Results:
- The proposed TSSC achieves a 42% higher read access pass yield compared to the conventional SPSC.
- Monte Carlo simulations confirm the effectiveness of the TSSC in minimizing threshold voltage mismatch effects.
- The TSSC demonstrates improved read yield at a nominal VDD of 1.0 V, albeit with a 1.75x increase in sensing time.
Conclusions:
- The timing-based split-path sensing circuit (TSSC) presents a viable solution for improving the read yield of STT-MRAMs in advanced technology nodes.
- The TSSC effectively mitigates threshold voltage mismatch issues, leading to significant performance gains.
- The proposed TSSC offers a promising approach for future STT-MRAM designs requiring high reliability and yield.
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