A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation...

Area of Science:

• Electrical Engineering
• Materials Science
• Computer Engineering

Background:

• High-bandwidth memory (HBM) requires advanced interconnect solutions for high-speed signaling.
• Conventional interposer channels face limitations in signal integrity and power efficiency.

Purpose of the Study:

• To propose and analyze a novel interposer channel structure with vertical tabbed vias.
• To enhance signal integrity and reduce power consumption in HBM systems.

Main Methods:

• Development of an analytical model for self- and mutual capacitance.
• Verification using 3D electromagnetic (EM) simulations.
• Analysis of electrical characteristics considering design parameters like via height, pitch, and channel gap.

Main Results:

• The proposed interposer channel demonstrates improved impedance, insertion loss, and reduced far-end crosstalk compared to conventional micro-strip and strip lines.
• At 8 Gbps, eye-width, eye-height, and eye-jitter were improved by 17.6%, 29%, and 9.56%, respectively, versus the strip line.
• Dynamic power consumption is reduced by approximately 28% due to minimized self-capacitance.

Conclusions:

• The novel vertical tabbed via interposer channel offers superior signal integrity and power efficiency for HBM.
• This design presents a viable solution for next-generation high-performance computing and memory systems.