A 746 nW ECG Processor ASIC Based on Ternary Neural Network.

Area of Science:

• Biomedical Engineering
• Integrated Circuit Design
• Machine Learning for Healthcare

Background:

• Long-term health monitoring requires efficient, low-power ECG analysis.
• Existing solutions often lack the capability for real-time detection of diverse abnormal cardiac rhythms (ACRs).

Purpose of the Study:

• To develop an ultra-low power application-specific integrated circuit (ASIC) for real-time ECG processing.
• To enable accurate detection and classification of multiple ACRs for wearable and implantable devices.

Main Methods:

• Designed an ECG processor ASIC using near-threshold logic in 65-nm CMOS technology.
• Implemented a derivative-based R-peak detection and two tiny machine learning classifiers (3-layer TNN and decision logic).
• Utilized minimal on-chip memory (1 KB) for parameters and data.

Main Results:

• Achieved ultra-low power consumption of 746 nW at 0.8 V and 2.5 kHz.
• Demonstrated high detection accuracy for 13 ACR types with 99.10% sensitivity and 99.5% specificity.
• The ASIC core area is 1.08 mm².

Conclusions:

• The developed ECG processor ASIC offers superior performance in terms of power efficiency and ACR detection capability compared to existing low-power designs.
• This technology supports advanced, long-term cardiac health monitoring through compact, efficient wearable or implantable devices.