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Fully integrated topological electronics.

Yuqi Liu1,2, Weidong Cao3, Weijian Chen1

  • 1Department of Electrical and Systems Engineering, Washington University, St Louis, MO, USA.

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|August 4, 2022
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Summary
This summary is machine-generated.

Topological insulators (TIs) are explored on integrated circuits (ICs) using standard semiconductor technology. This research demonstrates robust topological edge states on a designed circuit, paving the way for topological electronics.

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Area of Science:

  • Condensed Matter Physics
  • Electrical Engineering
  • Materials Science

Background:

  • Topological insulators (TIs) exhibit unique properties, attracting interest in photonics and acoustics.
  • Electronics offers advantages for constructing complex topological structures, enabling new research avenues.

Purpose of the Study:

  • To explore topological insulators (TIs) on an integrated circuit (IC) platform using standard complementary metal-oxide-semiconductor (CMOS) technology.
  • To design and simulate a fully integrated topological circuit chain based on the Su-Schrieffer-Heeger model.

Main Methods:

  • Design of a topological circuit chain using capacitively-coupled inductor-capacitor resonators.
  • Post-layout simulations on the physical layout to analyze topological features.
  • Evaluation of the topological edge state and its robustness against defects.

Main Results:

  • Demonstration of the existence of a topological edge state in the designed circuit.
  • Observation of remarkable robustness of the edge state against various defects.
  • Validation of the Su-Schrieffer-Heeger model in an integrated circuit context.

Conclusions:

  • The study confirms the feasibility of utilizing IC technology for exploring TIs.
  • The developed platform shows promise for future large-scale topological electronics.
  • This work bridges the gap between fundamental TI research and scalable electronic applications.