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Design of LDMOS Device Modeling Method Based on Neural Network.

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Researchers developed a new compact model for high-voltage LDMOS power transistors. This advanced model accurately predicts device behavior, including self-heating effects, crucial for efficient power electronics.

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Area of Science:

  • Electrical Engineering
  • Materials Science
  • Semiconductor Physics

Background:

  • Power semiconductor devices are essential for modern technology and a low-carbon society.
  • High-voltage Lateral Diffused Metal-Oxide-Semiconductor (LDMOS) transistors are critical components in various applications.

Purpose of the Study:

  • To develop and implement an accurate compact model for high-voltage LDMOS devices.
  • To improve the modeling of the drift region and incorporate self-heating effects.

Main Methods:

  • In-depth study of high-voltage LDMOS structure and physical mechanisms.
  • Utilized the industry-standard BSIM4 core model.
  • Modeled the drift region as a voltage-controlled variable resistor.
  • Employed Verilog-A language and neural network methods for compact model creation.

Main Results:

  • Successfully established a compact model for high-voltage LDMOS.
  • The improved model demonstrates enhanced fitting of output characteristics.
  • The model effectively accounts for the self-heating effect in LDMOS devices.

Conclusions:

  • The developed compact model provides a more accurate representation of high-voltage LDMOS behavior.
  • This advancement is vital for the design and optimization of power electronic systems.
  • Accurate modeling facilitates the realization of efficient and reliable power semiconductor devices.