Design of Convolutional Neural Network Processor Based on FPGA Resource Multiplexing Architecture.

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Acceleration

Background:

• Convolutional Neural Networks (CNNs) are increasingly complex, demanding substantial hardware resources and power.
• Deployment of CNNs is often limited by these resource constraints, hindering miniaturization and practicality.

Purpose of the Study:

• To propose a resource-efficient CNN processor design using an FPGA-based resource-multiplexing architecture.
• To reduce hardware resource and power consumption for CNNs without compromising performance.

Main Methods:

• Developed a CNN processor with a resource-multiplexing architecture on an FPGA.
• Utilized Verilog for FPGA deployment, optimizing with resource multiplexing and parallel processing.
• Tested a handwritten-digit-recognition CNN on the MNIST dataset.

Main Results:

• Achieved 97.3% prediction accuracy for handwritten digit recognition.
• System power consumption is 1.03 W, with the CNN module consuming only 0.03 W.
• Image prediction takes 68,139 clock cycles (340.7 us) at 200 MHz.

Conclusions:

• The proposed FPGA-based CNN processor demonstrates significant advantages in resource and power efficiency.
• This design offers a practical solution for deploying CNNs on resource-constrained platforms.
• The resource-multiplexing architecture effectively balances performance and efficiency for CNN acceleration.