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A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
Published on: August 28, 2018
Performance improvement in monolayered SnS2 double-gate field-effect transistors via point defect engineering
Haibo He1, Jianwei Zhao1, Pengru Huang2
1College of Material and Textile Engineering, Key Laboratory of Yarn Materials Forming and Composite Processing Technology, Jiaxing University, Jiaxing 314001, Zhejiang, P. R. China. heyy@zjxu.edu.cn.
Point defect engineering in monolayered tin disulfide (SnS2) enhances field-effect transistor (FET) performance. Doping with Se or Sn vacancies improves electronic properties for advanced, scaled electronics.
Area of Science:
- Materials Science
- Condensed Matter Physics
- Nanotechnology
Background:
- Monolayered SnS2 exhibits high carrier mobility and on/off ratio, making it suitable for short-channel field-effect transistors (FETs).
- Extending the scaling limit of channel length in FETs requires advanced material property modulation.
Purpose of the Study:
- To investigate the impact of point defect engineering on the electronic properties of monolayered SnS2.
- To simulate the performance limits of sub-5 nm double-gate FETs (DGFETs) based on engineered monolayered SnS2.
Main Methods:
- Density functional theory (DFT) combined with nonequilibrium Green's function (NEGF) formalism.
- Simulation of monolayered SnS2 supercells with substitutional Se dopants (SeS) and Sn vacancies (VSn).
- Analysis of electronic properties and device performance metrics for DGFETs with channel lengths down to 4.5 nm.
Main Results:
- SeS doping acts as an n-type dopant, while VSn defects induce p-type doping in monolayered SnS2.
- Engineered SeS-doped and VSn-doped SnS2 DGFETs showed remarkable improvements in on-state current (Ion), on/off ratio, delay time, and power-delay product.
- Achieved performance metrics meet the International Technology Roadmap for Semiconductors (ITRS) requirements for high-performance applications by 2028.
Conclusions:
- Point defect engineering is crucial for optimizing the electronic properties of monolayered SnS2.
- Customized defect design enables the development of high-performance, ultimately scaled electronic devices.
- This approach significantly advances the potential of SnS2 in next-generation FET applications.
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