Analysis of Pre-Driver and Last-Stage Power-Ground-Induced Jitter at Different PVT Corners

Area of Science:

• Electrical Engineering
• Semiconductor Device Physics
• Signal Integrity

Background:

• Power/ground (P/G) supply variations significantly impact integrated circuit performance.
• Jitter in output buffers affects data transmission reliability.
• Understanding power supply induced jitter (PSIJ) is critical for high-speed designs.

Purpose of the Study:

• To investigate power/ground supply-induced jitter (PGSIJ) in cascaded inverter output buffers.
• To compare jitter contributions from pre-driver and last-stage circuits.
• To analyze the impact of different P/G supply topologies on jitter.

Main Methods:

• Transient simulations of IO buffers under P/G supply voltage variations.
• Analysis across three process, voltage, and temperature (PVT) corners.
• Investigation of shared versus decoupled P/G supply topologies.

Main Results:

• Identified worst-case jitter corners based on PVT variations.
• Highlighted the necessity of including pre-driver behavior in IBIS-like models.
• Determined PGSIJ dependence on technology node and supply voltage noise.

Conclusions:

• Accurate PGSIJ analysis requires considering pre-driver circuit behavior.
• Designers must evaluate worst-case corners for signal and power integrity (SiPI) simulations.
• The superposition of PSIJ from different stages is amplitude-dependent and can exhibit nonlinear behavior.