Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors

Area of Science:

• Solid State Physics
• Semiconductor Device Physics
• Materials Science

Background:

• Sub-3-nm, 3-stacked nanosheet field-effect transistors (NSFETs) are crucial for next-generation electronics.
• Inner spacer thickness (T_IS) variation, arising from SiGe/Si selectivity, affects gate length (L_G) and device performance.

Purpose of the Study:

• To investigate the impact of inner spacer thickness variations (ΔT_IS) on NSFET performance using simulations.
• To analyze the distinct effects of top, middle, and bottom inner spacer thickness variations (ΔT_IS,T, ΔT_IS,M, ΔT_IS,B) separately.
• To examine the interplay between ΔT_IS and source/drain recess depth (T_SD) variations on parasitic bottom transistor (tr_pbt) control.

Main Methods:

• Utilized computer-aided design (CAD) simulation technology to model sub-3-nm, 3-stacked NSFETs.
• Investigated variations in inner spacer thickness (T_IS) and source/drain recess depth (T_SD).
• Analyzed the sensitivity of DC and AC performance metrics to different ΔT_IS scenarios.

Main Results:

• ΔT_IS significantly affects both DC and AC performance, with sensitivities varying based on the specific inner spacer (top, middle, or bottom).
• Source/drain recess depth variation (T_SD) exacerbates the impact of bottom inner spacer thickness variation (ΔT_IS,B) on parasitic bottom transistor performance.
• A T_SD of 5 nm increases off-state current (I_off) sensitivity to ΔT_IS,B by 22.5x in NFETs, highlighting the need for tight ΔT_IS,B control (<1 nm).

Conclusions:

• Reducing ΔT_IS,B is paramount for suppressing parasitic bottom transistor effects when T_SD variation is present.
• Minimizing ΔT_IS,T and ΔT_IS,M is crucial for reducing DC performance variation in the absence of T_SD variation.
• Tight control of ΔT_IS,B (<1 nm) is essential for achieving further scaling and yield enhancement in advanced NSFETs.