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Superior Quality Low-Temperature Growth of Three-Dimensional Semiconductors Using Intermediate Two-Dimensional Layers
Guanyu Zhou1, Rehan Younas1, Tian Sun1
1Department of Electrical Engineering, University of Notre Dame, Notre Dame, Indiana46556, United States.
Abstract:
The low-temperature growth of materials that support high-performance devices is crucial for advanced semiconductor technologies such as integrated circuits built using monolithic three-dimensional (3D) integration and flexible electronics. However, low growth temperature prohibits sufficient atomic diffusion and directly leads to poor material quality, imposing severe challenges that limit device performance. Here, we demonstrate superior quality growth of 3D semiconductors at growth temperatures reduced by >200 °C by using two-dimensional (2D) materials as intermediate layers to optimize the potential energy barrier for adatom diffusion. We reveal the benefits of maintaining, but reducing, the potential field through the 2D layer, which coupled with the inert surface of the 2D material lowers the kinetic barriers, enabling long-distance atomic diffusion and enhanced material quality at lower growth temperatures. As model systems, GaN and ZnSe, grown using WSe2 and graphene intermediate layers, exhibit larger grains, preferred orientation, reduced strain, and improved carrier mobility, all at temperatures lower by >200 °C compared to direct growth as characterized by diffraction, X-ray photoelectron spectroscopy, Raman, and Hall measurements. The realization of high-performance materials using 2D intermediate layers can enable transformative technologies under thermal budget restrictions, and the 2D/3D heterostructures could enable promising heterostructures for future device designs.
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