Anticipative QoS Control: A Self-Reconfigurable On-Chip Communication

Area of Science:

• Computer Engineering
• Integrated Circuit Design
• Network Architecture

Background:

• Network-on-Chip (NoC) architectures are crucial for modern integrated circuits.
• Existing NoCs face challenges in dynamic resource utilization and Quality of Service (QoS) management.
• Bidirectional communication and efficient packet handling are key performance bottlenecks.

Purpose of the Study:

• To propose a novel self-reconfigurable NoC architecture.
• To enhance performance and latency for prioritized packet transmission.
• To improve channel utilization and overall network efficiency.

Main Methods:

• Development of an Anticipative QoS Bidirectional-channel NoC (AQ-BiNoC) architecture.
• Implementation of anticipative Quality of Service (QoS) control by observing router requests two hops away.
• Integration of penetrative switch ability for rapid high-priority packet bypassing.
• Dynamic self-configuration of communication channels for bidirectional data flow.

Main Results:

• AQ-BiNoC demonstrates significant performance enhancements compared to conventional NoC designs.
• Improved channel bandwidth utilization due to flexible bidirectional communication.
• Reduced packet delivery latency, especially for high-priority traffic.
• Guaranteed better QoS for prioritized packets through dedicated virtual channels.

Conclusions:

• The proposed AQ-BiNoC architecture effectively addresses NoC performance limitations.
• Anticipative QoS control and penetrative switching are key innovations for enhanced network efficiency.
• AQ-BiNoC offers a promising solution for high-performance, QoS-aware on-chip communication.