A Novel Capacitorless 1T DRAM with Embedded Oxide Layer.

Area of Science:

• Semiconductor device physics
• Materials science
• Electrical engineering

Background:

• Capacitorless single transistor DRAM (1T DRAM) offers high integration density.
• Improving data retention time is crucial for advanced DRAM technologies.
• Scaling limitations exist in conventional 1T DRAM structures.

Purpose of the Study:

• To propose a novel vertical dual surrounding gate transistor structure for capacitorless 1T DRAM.
• To enhance the retention time and scalability of 1T DRAM devices.
• To investigate the impact of an embedded oxide layer on device performance.

Main Methods:

• Technology Computer-Aided Design (TCAD) simulations were employed.
• A novel vertical dual surrounding gate transistor architecture was designed.
• The effect of an embedded oxide layer on charge recombination was analyzed.

Main Results:

• The proposed structure demonstrates fast access times and random readability.
• The embedded oxide layer effectively reduces the recombination rate of stored holes and sensing electrons.
• Good retention characteristics and deep scaling potential were predicted.
• The novel structure shows improved scalability compared to conventional capacitorless 1T DRAM.

Conclusions:

• The novel vertical dual surrounding gate transistor with an embedded oxide layer is a promising candidate for future capacitorless 1T DRAM.
• This design addresses key challenges in retention time and scalability.
• The innovative use of an embedded oxide layer offers significant advantages for DRAM.