Detector Processor for a 5G Base Station.

Area of Science:

• Electrical Engineering
• Computer Engineering
• Telecommunications

Background:

• Nonlinear soft bit detection is critical for 5G base station uplink receivers, particularly for cell-edge users.
• High throughput and computational complexity remain significant challenges for existing soft-output detectors.
• Efficient detection methods are needed to improve the performance and scalability of 5G networks.

Purpose of the Study:

• To propose a low-cost, low-power parallel implementation of a soft-output detector.
• To reduce computational complexity and latency in nonlinear soft bit detection.
• To design a pipelined VLSI architecture for enhanced 5G uplink receivers.

Main Methods:

• Utilized sorted QR decomposition (SQRD) and the K-best breadth-first search algorithm.
• Implemented two optimization techniques: value saturation/truncation during PED computing and binary bit sorting for a reduced sample set.
• Designed a pipelined VLSI architecture using 28-nm digital CMOS technology (SMIC).

Main Results:

• Achieved a peak throughput of 6400 Mbps at 800 MHz.
• Consumed 153 K gates (including flip-flops) in SMIC's 28-nm technology.
• Demonstrated a 32% cost reduction compared to published reference designs.

Conclusions:

• The proposed detector offers a significant reduction in computational complexity and latency.
• The VLSI architecture provides a cost-effective and power-efficient solution for 5G uplink receivers.
• This work addresses key challenges in nonlinear soft bit detection for improved 5G performance.