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SRAM-Based CIM Architecture Design for Event Detection.

Muhammad Bintang Gemintang Sulaiman1, Jin-Yu Lin1, Jian-Bai Li1

  • 1Industrial Technology Research Institute, 195, Section 4, Zhongxing Road, Zhudong Township, Hsinchu 310401, Taiwan.

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|October 27, 2022
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Summary
This summary is machine-generated.

This study introduces a hierarchical AI architecture using computing-in-memory (CIM) to reduce power consumption in AIoT applications. The CIM-aware design achieves high accuracy on gesture and image datasets while optimizing energy efficiency for edge devices.

Keywords:
artificial internet of thingscomputing in memoryconvolutional neural network

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Area of Science:

  • Artificial Intelligence
  • Computer Architecture
  • Deep Learning Hardware Acceleration

Background:

  • Convolutional Neural Networks (CNNs) are computationally intensive, limiting their use in energy-constrained hardware accelerators.
  • Computing-in-Memory (CIM) offers a promising solution by performing computations directly within memory (SRAM), reducing data movement and energy use.
  • Existing CIM architectures show potential for matrix-vector multiplication but require software-hardware co-design for efficient AI edge deployment.

Purpose of the Study:

  • To design and evaluate a hierarchical AI architecture optimized for low power consumption in AIoT applications.
  • To address the hardware limitations of SRAM-based CIM macros for efficient weight mapping on AI edge devices.
  • To develop a CIM-aware algorithm and profiling tool for system efficiency analysis.

Main Methods:

  • A hierarchical AI architecture was designed using a software and hardware co-design approach.
  • An SRAM-based CIM accelerator was implemented, considering hardware constraints for AI edge deployment.
  • A CIM-aware algorithm with 4-bit activation and 8-bit weight was evaluated on hand gesture and CIFAR-10 datasets.
  • A profiling tool was developed to analyze the efficiency of the proposed architecture.

Main Results:

  • The CIM-aware algorithm achieved 99.70% accuracy on the hand gesture dataset and 70.58% on the CIFAR-10 dataset.
  • The system operated at 100 MHz, processing 662 frames per second (FPS) with 37.6% processing unit utilization.
  • The proposed design demonstrated a low power consumption of 0.853 mW.

Conclusions:

  • The developed hierarchical AI architecture effectively optimizes end-to-end system power for AIoT applications.
  • SRAM-based CIM technology, coupled with a CIM-aware algorithm, significantly enhances energy efficiency for AI edge devices.
  • The co-design approach successfully maps CNN models onto hardware limitations, achieving high performance and low power consumption.