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Metal-Semiconductor Junctions01:24

Metal-Semiconductor Junctions

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The contact of metal and semiconductor can lead to the formation of a junction with either Schottky or Ohmic behavior.
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A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
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The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) plays a pivotal role in modern electronics thanks to its versatility and efficiency in controlling electrical currents. This device, also known as IGFET, MISFET, and MOSFET, has three main terminals: the Source, Drain, and Gate. MOSFETs are classified into n-channel or p-channel types based on the doping characteristics of their substrate and the source or drain regions.
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Related Experiment Video

Updated: Aug 23, 2025

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Reliable metal-graphene contact formation process flows in a CMOS-compatible environment.

M Elviretti1, M Lisker1,2, R Lukose1

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This summary is machine-generated.

Optimizing graphene-metal contacts is key for microelectronics. This study shows specific patterning and passivation techniques achieve low contact resistance, enabling graphene

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Area of Science:

  • Materials Science
  • Solid State Physics
  • Microelectronics Engineering

Background:

  • Graphene holds significant promise for advanced electronic and photonic devices.
  • Efficient integration into existing manufacturing processes, like CMOS, requires optimized interfaces.
  • Low contact resistance between graphene and metals is a critical bottleneck for device performance.

Purpose of the Study:

  • To investigate the impact of graphene patterning and passivation strategies on contact resistance.
  • To optimize graphene-metal contact formation within an 8-inch wafer pilot-line environment.
  • To establish reproducible methods for achieving low contact resistivity in graphene-based devices.

Main Methods:

  • Utilized an 8-inch wafer pilot-line for CMOS integration studies.
  • Employed Transmission Line Measurement (TLM) to quantify contact resistance.
  • Investigated various graphene patterning techniques and passivation methods.
  • Applied post-processing treatments, including annealing, to enhance contact properties.

Main Results:

  • Demonstrated reproducible formation of graphene-metal contacts with contact resistivity as low as 660 Ω μm.
  • Achieved a low sheet resistance of 1.8 kΩ/□ for the graphene channel.
  • Identified specific graphene patterning and passivation approaches that significantly reduce contact resistance.

Conclusions:

  • Optimized graphene patterning and passivation are crucial for minimizing contact resistance.
  • The developed methods facilitate the integration of graphene into CMOS technology.
  • Achieving low contact resistance paves the way for high-performance graphene-based electronic and photonic devices.