Reliable metal-graphene contact formation process flows in a CMOS-compatible environment

Area of Science:

• Materials Science
• Solid State Physics
• Microelectronics Engineering

Background:

• Graphene holds significant promise for advanced electronic and photonic devices.
• Efficient integration into existing manufacturing processes, like CMOS, requires optimized interfaces.
• Low contact resistance between graphene and metals is a critical bottleneck for device performance.

Purpose of the Study:

• To investigate the impact of graphene patterning and passivation strategies on contact resistance.
• To optimize graphene-metal contact formation within an 8-inch wafer pilot-line environment.
• To establish reproducible methods for achieving low contact resistivity in graphene-based devices.

Main Methods:

• Utilized an 8-inch wafer pilot-line for CMOS integration studies.
• Employed Transmission Line Measurement (TLM) to quantify contact resistance.
• Investigated various graphene patterning techniques and passivation methods.
• Applied post-processing treatments, including annealing, to enhance contact properties.

Main Results:

• Demonstrated reproducible formation of graphene-metal contacts with contact resistivity as low as 660 Ω μm.
• Achieved a low sheet resistance of 1.8 kΩ/□ for the graphene channel.
• Identified specific graphene patterning and passivation approaches that significantly reduce contact resistance.

Conclusions:

• Optimized graphene patterning and passivation are crucial for minimizing contact resistance.
• The developed methods facilitate the integration of graphene into CMOS technology.
• Achieving low contact resistance paves the way for high-performance graphene-based electronic and photonic devices.