Sensing Remote Bulk Defects through Resistance Noise in a Large-Area Graphene Field-Effect Transistor

The substrate plays a crucial role in determining the transport and low-frequency noise behavior of graphene field-effect devices. Typically, a heavily doped Si/SiO₂ substrate is used to fabricate these devices for efficient gating. Trapping-detrapping processes close to the graphene/substrate interface are the dominant sources of resistance fluctuations in the graphene channel, while Coulomb fluctuations arising due to any remote charge fluctuations inside the bulk of the substrate are effectively screened by the heavily doped substrate. Here, we present the electronic transport and low-frequency noise characteristics of a large-area CVD graphene field-effect transistor (FET) prepared on a lightly doped Si/SiO₂ substrate (N_A ≈ 10¹⁵ cm^-3). Through a systematic characterization of transport, noise, and capacitance at various temperatures, we reveal that the remote Si/SiO₂ interface can affect the charge transport in graphene severely and any charge fluctuations inside the bulk of the silicon substrate can be sensed by the graphene channel. The resistance (R) vs back-gate voltage (V_bg) characteristics of the device show a hump around the depletion region formed at the SiO₂/Si interface, confirmed by the capacitance (C)-voltage (V) measurement. A low-frequency noise measurement on these fabricated devices shows a peak in the noise amplitude close to the depletion region. This indicates that due to the absence of any charge layer at the Si/SiO₂ interface, the screening ability decreases, and as a consequence, any fluctuations in the deep-level Coulomb impurities inside the silicon substrate can be observed as noise in resistance in the graphene channel via mobility fluctuations. The noise behavior on ionic liquid-gated graphene on the same substrate exhibits no such peak in noise and can be explained by the interfacial trapping-detrapping processes close to the graphene channel. Our study will definitely be useful for integrating graphene with the existing silicon technology, in particular, for high-frequency applications.