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SCA: Search-Based Computing Hardware Architecture with Precision Scalable and Computation Reconfigurable Scheme.

Liang Chang1, Xin Zhao1, Jun Zhou1

  • 1School of Information and Communication Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China.

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Summary
This summary is machine-generated.

This study introduces a novel search-based computing scheme for deep neural networks (DNNs) on hardware accelerators. The proposed Search-based Computing Architecture (SCA) enhances computational efficiency and scalability while reducing memory bottlenecks.

Keywords:
computational utilizationlook-up tableprecision scalablereconfigurablesearch-based computing

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Area of Science:

  • Computer Engineering
  • Artificial Intelligence Hardware
  • Deep Learning Systems

Background:

  • Deep neural networks (DNNs) demand substantial computational resources and memory access, leading to inefficiencies in hardware accelerators like GPUs, FPGAs, and ASICs.
  • Existing lookup-table (LUT)-based accelerators face limitations in computational precision and scalability.
  • Frequent off-chip memory access creates bottlenecks, reducing overall hardware efficiency.

Purpose of the Study:

  • To propose a novel search-based computing scheme to improve the efficiency of DNN inference on hardware accelerators.
  • To address the limitations of traditional LUT-based accelerators regarding precision and scalability.
  • To reduce hardware resource overhead and data movement bottlenecks.

Main Methods:

  • Developed a search-based computing scheme that replaces traditional multiplication with a search operation.
  • Implemented a reconfigurable computing strategy to adapt to various convolution kernel sizes, enhancing scalability.
  • Designed the Search-based Computing Architecture (SCA) with an on-chip storage mechanism to minimize off-chip memory interactions.

Main Results:

  • The SCA architecture achieves high computational utilization: 92% for 4-bit, 96% for 8-bit, and 98% for 16-bit precision.
  • The proposed scheme supports multiple bit-widths for different DNN applications.
  • Achieved a four-fold improvement in efficiency compared to state-of-the-art LUT-based architectures.

Conclusions:

  • The search-based computing scheme offers a significant improvement in DNN hardware accelerator efficiency.
  • The SCA architecture effectively mitigates memory bandwidth pressure and enhances scalability.
  • This approach provides a flexible and efficient solution for deploying DNNs on hardware accelerators with varying precision requirements.