Steep-Slope Transistor with an Imprinted Antiferroelectric Film

Area of Science:

• Semiconductor device physics
• Materials science for electronics

Background:

• Negative capacitance (NC) offers a pathway to overcome the Boltzmann limit in transistors by internally boosting voltage.
• Stabilizing NC requires integrating a dielectric (DE) with a ferroelectric (FE) film in a heterostructure.
• Multidomain hafnia presents challenges, reducing charge boosting and increasing operating voltage due to depolarization and voltage division effects.

Purpose of the Study:

• To demonstrate core approaches for gate stack engineering in energy-efficient device technology using transient NC.
• To overcome limitations of traditional NC implementations in multidomain materials.

Main Methods:

• Fabrication of gate stacks incorporating imprinted antiferroelectric materials.
• Integration of high dielectric (DE) to ferroelectric (FE) capacitance ratios (C_DE/C_FE).
• Electrical characterization of fabricated transistors under transient NC conditions.

Main Results:

• Achieved low subthreshold slopes below 20 mV/dec.
• Demonstrated low voltage operation at 0.5 V.
• Observed fast operation with a 20 ns switching time.
• Exhibited hysteresis-free drain current-gate voltage (Id-Vg) characteristics.
• Attained high endurance exceeding 10^12 cycles.

Conclusions:

• The developed transient NC approach significantly enhances device performance.
• This technology enables rapid implementation of NC for high-speed switching applications.
• The study paves the way for significantly improved energy efficiency in electronic devices.