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The brain processes sensory information rapidly due to parallel processing, which involves sending data across multiple neural pathways at the same time. This method allows the brain to manage various sensory qualities, such as shapes, colors, movements, and locations, all concurrently. For instance, when observing a forest landscape, the brain simultaneously processes the movement of leaves, the shapes of trees, the depth between them, and the various shades of green. This enables a quick and...
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In a three-phase circuit, line loss is an indicator of energy dissipated as heat due to the resistance of transmission lines. To address this, incorporating transformers into the system—a step-up transformer at the source and a step-down transformer at the load—is a strategic solution. Two three-phase transformers are introduced to improve this.
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Managing signal sampling rates is essential in digital signal processing to maintain signal integrity. A decimated signal, characterized by a reduced frequency range due to its lower sampling rate, can be upsampled by inserting zeros between each sample. This upsampling process expands the original spectrum and introduces repeated spectral replicas at intervals dictated by the new Nyquist frequency. To refine this zero-inserted sequence, it is passed through a lowpass filter with a cutoff...
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Related Experiment Video

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HybriDC: A Resource-Efficient CPU-FPGA Heterogeneous Acceleration System for Lossless Data Compression.

Puguang Liu1, Ziling Wei1, Chuan Yu1

  • 1College of Computer Science and Technology, National University of Defense Technology, Changsha 410073, China.

Micromachines
|November 24, 2022
PubMed
Summary

HybriDC is a novel CPU-FPGA system that efficiently accelerates lossless data compression. It optimizes hardware design for better resource use and achieves superior memory efficiency and power savings compared to traditional methods.

Keywords:
CPU-FPGA heterogeneous accelerationLZ4lossless data compressionperformance modelingresource efficiency

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Area of Science:

  • Computer Engineering
  • Data Compression Algorithms
  • Hardware Acceleration

Background:

  • Lossless data compression is computationally intensive, leading to high CPU overhead.
  • Existing FPGA accelerators often suffer from imbalanced resource utilization and limited practicality.
  • There is a need for efficient, adaptable hardware solutions for data compression workloads.

Purpose of the Study:

  • To propose HybriDC, an adaptive, resource-efficient CPU-FPGA heterogeneous acceleration system for lossless data compression.
  • To develop a universal framework offering application compatibility and performance scalability for compression acceleration.
  • To optimize hardware compression kernel design through a performance-resource model and resource-balanced principles.

Main Methods:

  • Developed a performance-resource model for compression algorithms to guide hardware kernel design.
  • Fine-tuned compression algorithm parameters based on a resource-balanced design principle, reducing block RAM usage by 32% for the LZ4 kernel.
  • Implemented a memory-efficient parallel hash table with an extra checksum for parallel processing and improved compression ratio.

Main Results:

  • The HybriDC LZ4 compression kernel demonstrates state-of-the-art memory efficiency, 2.5-4x better than existing designs.
  • Achieved comparable compression ratios with significantly improved memory usage.
  • The four-kernel HybriDC prototype showed a threefold power efficiency advantage over the standard LZ4 algorithm.

Conclusions:

  • HybriDC offers an adaptive and resource-efficient heterogeneous acceleration system for lossless data compression.
  • The system provides excellent scalability in terms of resource utilization and end-to-end throughput.
  • HybriDC significantly enhances memory efficiency and power savings for data compression tasks.