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Updated: Aug 16, 2025

Optimized Fabrication Procedure for High-Quality Graphene-based Moiré Superlattice Devices
Published on: July 11, 2025
Jianhan Fan1, Sen Lu2, Jianxiao Zou1,3
1School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China.
This study introduces a moiré-based mark for precise wafer bonding alignment. The digital grating and moiré fringes enable highly stable and accurate offset calculations for improved semiconductor manufacturing.
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