High-Density 1R/1W Dual-Port Spin-Transfer Torque MRAM

Area of Science:

• * Electrical Engineering and Computer Science
• * Materials Science and Engineering

Background:

• * Spin-transfer torque magnetic random-access memory (STT-MRAM) offers non-volatility and high integration density but faces challenges in write latency and read/write stability tradeoffs.
• * Existing multi-port STT-MRAM designs improve functionality but increase area due to additional transistors per bit cell.

Purpose of the Study:

• * To propose an area-efficient 1R/1W dual-port STT-MRAM design.
• * To address simultaneous access conflicts in bitline-sharing architectures.
• * To optimize read stability and write ability in dual-port configurations.

Main Methods:

• * Development of a 1R/1W dual-port STT-MRAM architecture utilizing bitline sharing between adjacent cells.
• * Implementation of a bit-interleaving strategy with extended interleaving distances and sufficient word lines per bank to mitigate access conflicts.
• * Performance evaluation using a 45 nm process technology.

Main Results:

• * The proposed dual-port STT-MRAM design achieves a 25% area improvement compared to prior dual-port designs.
• * Demonstrates a 15% reduction in read power and a 19% enhancement in read-disturb margin relative to standard single-port STT-MRAM.
• * Successfully alleviates simultaneous access conflicts through the proposed architecture.

Conclusions:

• * The novel bitline-sharing dual-port STT-MRAM design offers a compelling solution for area-constrained memory applications.
• * This approach effectively balances performance metrics like read power and stability with reduced silicon footprint.
• * The bit-interleaving architecture is crucial for managing conflicts in shared bitline configurations.