Dielectric-Engineered High-Speed, Low-Power, Highly Reliable Charge Trap Flash-Based Synaptic Device for Neuromorphic...

Area of Science:

• Materials Science
• Computer Engineering
• Artificial Intelligence

Background:

• The big-data era necessitates power-efficient computing beyond the Von Neumann architecture.
• Neuromorphic computing, inspired by the brain, offers a solution for reduced power consumption, with synaptic devices being crucial.
• Existing synaptic devices often lack linearity and symmetry, limiting their application.

Purpose of the Study:

• To develop a power-efficient and reliable synaptic transistor for neuromorphic computing.
• To address the limitations of linearity and symmetry in current synaptic devices.
• To demonstrate the efficacy of the proposed device in AI applications.

Main Methods:

• Fabrication of a charge-trap flash (CTF) transistor with a novel Al2O3/Ta2O5/Al2O3 engineered gate stack.
• Utilizing precise bias and short, low-voltage pulses for synaptic weight modulation.
• Testing the device's performance in terms of linearity, symmetry, and endurance.

Main Results:

• The engineered gate stack enabled precise control of conductance with over 6 bits of precision.
• Achieved highly linear and symmetric conductance modulation using short (25 ns) identical pulses.
• Demonstrated low power consumption and high reliability.

Conclusions:

• The developed CTF-based synaptic transistor is a promising candidate for efficient neuromorphic computing.
• The novel gate stack design overcomes key limitations of existing synaptic devices.
• The device achieved high learning accuracy on the MNIST dataset, validating its potential for AI applications.