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Brain State-dependent Brain Stimulation with Real-time Electroencephalography-Triggered Transcranial Magnetic Stimulation

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Power-efficientin vivobrain-machine interfaces via brain-state estimation.

Daniel Valencia^1,2, Gianluca Leone³, Nicholas Keller¹

¹Department of Electrical and Computer Engineering, San Diego State University, San Diego, United States of America.

Journal of Neural Engineering

|January 16, 2023

Summary

This summary is machine-generated.

This study introduces an intention-aware brain-machine interface (BMI) that significantly reduces power consumption in implanted devices. This innovation enhances the longevity and performance of neural implants for individuals with neurological disorders.

Keywords:

application-specific integrated circuits brain–machine interfaces neural signal processing

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Last Updated: Aug 14, 2025

Brain State-dependent Brain Stimulation with Real-time Electroencephalography-Triggered Transcranial Magnetic Stimulation

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Published on: August 20, 2019

Assessment and Communication for People with Disorders of Consciousness

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A Single-Channel and Non-Invasive Wearable Brain-Computer Interface for Industry and Healthcare

A Single-Channel and Non-Invasive Wearable Brain-Computer Interface for Industry and Healthcare

Published on: July 7, 2023

Area of Science:

Biomedical Engineering
Neuroscience
Electrical Engineering

Background:

Brain-machine interfaces (BMIs) offer life-improving potential for individuals with spinal cord injury and neurological disorders.
Reducing power consumption in implanted BMIs is critical for device longevity and user benefit.

Purpose of the Study:

To present the first hardware realization of an *in vivo* intention-aware interface using brain-state estimation.
To decrease the power demands of brain-implanted interfaces.

Main Methods:

Developed an intention-aware interface incorporating brain-state estimation.
Designed and synthesized an application-specific integrated circuit (ASIC) for multi-unit spike detection.
Utilized a standard 180 nm CMOS process for ASIC fabrication.

Main Results:

The *in vivo* power consumption was reduced by over 1.8× compared to existing systems.
The developed ASIC achieved the lowest power consumption (0.63 µW/channel) among current *in vivo* ASIC realizations.
The interface occupies a minimal silicon area of 0.03 mm².

Conclusions:

This work presents a practical approach for asynchronous BMIs.
The proposed interface reduces BMI power consumption and improves neural decoding performance over conventional synchronous BMIs.