Heterogeneous Integration of Atomically-Thin Indium Tungsten Oxide Transistors for Low-Power 3D Monolithic...

Area of Science:

• Materials Science
• Electrical Engineering
• Nanotechnology

Background:

• Traditional planar transistor structures face limitations in scaling and power efficiency.
• Heterogeneous integration of different semiconductor materials is crucial for advanced electronic devices.

Purpose of the Study:

• To demonstrate a novel vertically-stacked thin film transistor (TFT) architecture for complementary inverter applications.
• To evaluate the performance of amorphous indium tungsten oxide (a-IWO) n-channel TFTs integrated with p-channel polycrystalline silicon (poly-Si) TFTs.

Main Methods:

• Fabrication of a vertically-stacked TFT architecture using p-channel poly-Si and n-channel a-IWO.
• Characterization of the electrical properties of the a-IWO TFT, including mobility, subthreshold swing, leakage current, and on/off ratio.
• Evaluation of the performance of the complementary inverter, including voltage gain and noise margin.

Main Results:

• The a-IWO TFT exhibited high mobility (24 cm²/V·s), near-ideal subthreshold swing (63 mV/dec), low leakage current (<10⁻¹³ A), high on/off ratio (>10⁹), and minimal hysteresis.
• The n-channel a-IWO TFT characteristics were well-matched with p-channel poly-Si TFTs.
• The complementary inverter achieved a high voltage gain (152 V/V) at a low supply voltage (1.5 V) with a noise margin up to 80% and pico-watt static power consumption.

Conclusions:

• The novel vertically-stacked TFT architecture enables high energy-efficiency and increased circuit density.
• This technology is suitable for next-generation semiconductor applications requiring advanced complementary metal-oxide-semiconductor (CMOS) technology.
• The integration of a-IWO offers a promising pathway for developing high-performance, low-power electronic devices.