Search research articles

ABOUT JoVE

Overview Leadership Blog JoVE Help Center

AUTHORS

Publishing Process Editorial Board Scope & Policies Peer Review FAQ Submit

LIBRARIANS

Testimonials Subscriptions Access Resources Library Advisory Board FAQ

RESEARCH

JoVE Journal Methods Collections JoVE Encyclopedia of Experiments Archive

EDUCATION

JoVE Core JoVE Business JoVE Science Education JoVE Lab Manual Faculty Resource Center Faculty Site

Terms & Conditions of Use

Related Concept Videos

MOSFET: Enhancement Mode

MOSFET: Enhancement Mode

Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...

MOS Capacitor

MOS Capacitor

A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
The metal gate is typically made from highly conductive materials such as aluminum or polysilicon. Beneath the metal gate lies a thin layer of...

Relation between Mathematical Equations and Block Diagrams

Relation between Mathematical Equations and Block Diagrams

In a spring-mass-damper system, the second-order differential equation describes the dynamic behavior of the system. When transformed into the Laplace domain under zero initial conditions, this equation can be effectively analyzed and manipulated. The transformation into the Laplace domain converts differential equations into algebraic equations, simplifying the process of isolating the output.

Signal Flow Graphs

Signal Flow Graphs

Signal-flow graphs offer a streamlined and intuitive approach to representing control systems, providing an alternative to traditional block diagrams. These graphs use branches to symbolize systems and nodes to represent signals, effectively illustrating the relationships and interactions within the system.
In a signal-flow graph, branches denote the system's transfer functions, while nodes represent the signals. The direction of signal flow is indicated by arrows, with the corresponding...

Block Diagram Reduction

Block Diagram Reduction

The process of deriving the transfer function of a control system often involves reducing its block diagram to a single block. This simplification can be achieved through a series of strategic operations, including relocating branch points and comparators. These operations preserve the overall function of the system while allowing for easier manipulation and combination of blocks.
The first step in this process is the identification and relocation of a branch point. A branch point, where a...

Design Example: Capacitance Multiplier Circuit

Design Example: Capacitance Multiplier Circuit

In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.

You might also read

Related Articles

Articles linked to this work by shared authors, journal, and citation graph.

Sort by

Same author

Intelligent financial forecasting using transformers, neuro-symbolic AI, and agent-based systems.

Scientific reports·2026

Same author

Real time urban traffic prediction using RFID and a hybrid LSTM random forest model.

Scientific reports·2025

Same author

Design and implementation of a smart earthquake rescue robot to enhance rescue operations.

Scientific reports·2025

Same author

Design of a low-delay 4-bit parallel prefix adder using QCA technology.

Scientific reports·2025

Same author

Mitigating side channel attacks on FPGA through deep learning and dynamic partial reconfiguration.

Scientific reports·2025

Search research articles

Related Experiment Video

Updated: Aug 13, 2025

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

Published on: June 3, 2015

Efficient design and analysis of secure CMOS logic through logic encryption.

Sai Srinivas Chandra¹, R Jagadeesh Kannan², B Saravana Balaji³

¹Department of CSE, Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kancheepuram, Chennai, 600127, India.

Scientific Reports

|January 20, 2023

Summary

This summary is machine-generated.

This study introduces a novel transistor-level logic encryption method for CMOS gates to enhance hardware security. The proposed technique significantly reduces design overheads like area and power, improving integrated circuit protection against intellectual property piracy.

More Related Videos

Gene Digital Circuits Based on CRISPR-Cas Systems and Anti-CRISPR Proteins

Gene Digital Circuits Based on CRISPR-Cas Systems and Anti-CRISPR Proteins

Published on: October 18, 2022

Design and Analysis for Fall Detection System Simplification

Design and Analysis for Fall Detection System Simplification

Published on: April 6, 2020

Related Experiment Videos

Last Updated: Aug 13, 2025

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

Published on: June 3, 2015

Gene Digital Circuits Based on CRISPR-Cas Systems and Anti-CRISPR Proteins

Gene Digital Circuits Based on CRISPR-Cas Systems and Anti-CRISPR Proteins

Published on: October 18, 2022

Design and Analysis for Fall Detection System Simplification

Design and Analysis for Fall Detection System Simplification

Published on: April 6, 2020

Area of Science:

Electrical Engineering
Computer Engineering
Hardware Security

Background:

Globalization in semiconductor design necessitates robust hardware security measures.
Intellectual property (IP) piracy and malicious tampering are significant threats in integrated circuit (IC) design.
Existing logic encryption methods often introduce substantial overheads in area, power, and performance.

Purpose of the Study:

To propose a novel transistor-level logic encryption method for CMOS gates.
To achieve a trade-off between security and design metrics (area, power, performance).
To enhance hardware security against IP piracy and reverse engineering.

Main Methods:

Development of a transistor-level logic encryption technique for CMOS gates.
Focus on security as the primary objective while optimizing design parameters.
Implementation and evaluation of encrypted key gates.

Main Results:

The proposed logic encryption method significantly reduces design overheads.
Average reductions observed: 42.94% in area, 37.37% in power, 26.79% in delay, and 50.96% in energy.
Demonstrated improved security with reduced overhead compared to existing topologies.

Conclusions:

The novel transistor-level logic encryption offers an effective solution for hardware security.
The method successfully balances security needs with reduced design overheads.
This approach provides a promising direction for protecting IC designs in a globalized industry.