An Automatic Detection Method for Cutting Path of Chips in Wafer

Area of Science:

• Semiconductor Manufacturing
• Image Processing
• Robotics

Background:

• Wafer imaging is sensitive to illumination and chip quality variations, leading to defects like uneven brightness.
• These defects negatively impact the accuracy of wafer cutting path positioning.
• Accurate positioning is crucial for maximizing chip cutting yield in semiconductor manufacturing.

Purpose of the Study:

• To develop an automated chip-cutting path-planning method for wafer images in the Glass Passivation Parts (GPPs) process without relying on external markers.
• To address challenges posed by varying illumination and chip surface qualities.
• To enhance the accuracy and efficiency of wafer dicing.

Main Methods:

• Brightness calibration of wafer images to improve quality and highlight chip features.
• Template matching algorithm to identify chip regions and their centers of gravity.
• Utilizing geometric features (interlayer) within chip regions as auxiliary locators.
• Employing an improved Random Sample Consensus (RANSAC) algorithm for precise interlayer fitting and outlier removal.

Main Results:

• Brightness calibration significantly improved image quality and chip feature visibility.
• Average deviation of chip region gravity coordinates in the x-direction was 2.82 pixels.
• The improved RANSAC algorithm achieved an average fitting error of 0.8 pixels for interlayer detection, outperforming the least squares method (LSM).

Conclusions:

• The proposed method accurately and quickly determines cutting paths, adapting to environmental brightness changes and diverse chip qualities.
• The algorithm effectively enhances chip cutting yield by improving positioning accuracy.
• This automated approach offers a robust solution for precise wafer dicing in the GPPs process.