Dead Zone Minimization Using Variable-Delay Element in CP-PLL for 5G Applications.

Area of Science:

• Electrical Engineering
• Integrated Circuit Design
• Signal Processing

Background:

• The dead zone in phase-frequency detectors (PFDs) is a critical performance bottleneck for phase-locked loops (PLLs).
• Existing fixed-delay elements reduce dead zone but introduce timing imbalances, increasing PLL phase noise.
• This necessitates a novel approach to mitigate PFD dead zone without compromising PLL spectral purity.

Purpose of the Study:

• To introduce and analyze a new variable-delay element (VDE) for PFDs.
• To reduce the dead zone of the PFD and consequently decrease the phase noise of the PLL.
• To evaluate the performance of a PLL incorporating the proposed PFD for 5G applications.

Main Methods:

• Incorporation of a novel variable-delay element (VDE) into the PFD architecture.
• Analysis of the proposed PFD integrated within a PLL using Cadence Virtuoso.
• Performance evaluation using 90 nm CMOS technology at a 3.5 GHz operating frequency.

Main Results:

• Achieved a significantly reduced dead zone of 110.5 ps.
• Demonstrated a low phase noise of -148.89 dBc/Hz at 1 MHz offset.
• Reported a fast lock time of 6.01 µs and low power consumption of 0.056 mW.

Conclusions:

• The proposed VDE effectively reduces PFD dead zone, leading to lower PLL phase noise.
• The integrated PLL exhibits excellent performance metrics suitable for high-frequency 5G applications.
• This VDE-enhanced PFD offers a promising solution for advanced wireless communication systems.