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Related Concept Videos

Design Example: Capacitance Multiplier Circuit01:20

Design Example: Capacitance Multiplier Circuit

889
In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
889

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High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor.

Zhongjie Guo1, Yangle Wang1, Ruiming Xu1

  • 1Department of Electronic Engineering, Xi'an University of Technology, No. 5 Jinhua South Road, Xi'an 710054, China.

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Summary
This summary is machine-generated.

This study introduces a novel high-speed analog-to-digital converter (ADC) design for CMOS image sensors (CIS), overcoming speed limitations. The new method significantly boosts conversion speed, enabling high frame rate applications.

Keywords:
CMOS image sensordifferential ramplevel encodingtime-to-digital conversiontwo-step

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Area of Science:

  • Electrical Engineering
  • Materials Science

Background:

  • Traditional analog-to-digital converters (ADCs) in CMOS image sensors (CIS) face speed limitations, hindering high frame rate applications.
  • Existing single-slope and serial two-step ADCs do not meet the demanding speed requirements of modern industrial CIS applications.

Purpose of the Study:

  • To propose a high-speed, fully differential two-step ADC design method for CMOS image sensors.
  • To address the speed limitations of traditional ADCs and enable high frame rate CIS applications.

Main Methods:

  • Developed a novel ADC design based on differential ramp and time-to-digital conversion (TDC) technology.
  • Implemented a parallel conversion mode and a level-coding-based TDC for improved performance.
  • Designed, laid out, and verified the circuit on a 55 nm 1P4M CMOS platform.

Main Results:

  • Achieved a 12-bit ADC with a conversion time of 480 ns at a 100 MHz clock frequency.
  • Demonstrated low power consumption (62 μW), excellent linearity (DNL ±0.6 LSB, INL +1.2/-1.4 LSB), and high SNDR (70.08 dB).
  • Achieved over 52% increase in conversion speed compared to advanced single-slope ADCs.

Conclusions:

  • The proposed differential ramp and level-coding TDC based two-step ADC offers an effective solution for high frame rate CIS.
  • This design enables large area arrays with high frame rates, meeting industrial application demands.
  • The method provides a significant advancement in ADC technology for high-performance image sensing.