CMOS-compatible ising machines built using bistable latches coupled through ferroelectric transistor arrays.

Area of Science:

• Spintronics and Neuromorphic Computing
• Solid-State Devices and Circuit Design

Background:

• Compact and scalable Ising machines are essential for accelerating intractable computational problems.
• Current Ising machine designs face scalability challenges, particularly in implementing spin coupling networks compatible with CMOS technology.

Purpose of the Study:

• To propose a novel Ising machine platform leveraging CMOS-compatible components for enhanced scalability.
• To address the bottleneck in spin-spin interaction implementation for Ising machines.

Main Methods:

• Utilizing compact bi-stable CMOS-latches as classical Ising spins.
• Employing ferroelectric-HfO2-based Ferroelectric FETs (FeFETs) as scalable coupling elements.
• Experimental demonstration of prototype building blocks and simulation-based evaluation of scaling behavior.

Main Results:

• Successful experimental demonstration of the proposed Ising machine's fundamental components.
• Evaluation of the system's scaling potential through simulations, indicating promising scalability.
• Validation of CMOS-process compatibility for both spin and coupling elements.

Conclusions:

• The proposed Ising machine platform offers a viable pathway towards CMOS-compatible designs.
• The use of FeFETs as coupling elements effectively overcomes scalability challenges in Ising machines.
• This work paves the way for practical, large-scale Ising hardware acceleration.