Implementation of a motion estimation algorithm for Intel FPGAs using OpenCL.

Area of Science:

• Computer Engineering
• Hardware Acceleration
• Video Processing

Background:

• Motion Estimation (ME) is crucial for video encoding but computationally intensive.
• Traditional FPGA implementations use complex Hardware Description Languages (HDLs) like VHDL and Verilog.
• Higher-level languages are sought for more accessible FPGA application development.

Purpose of the Study:

• To assess the expressiveness of OpenCL for FPGA application development.
• To implement and evaluate a Block Matching Motion Estimation (BMME) algorithm using OpenCL on Intel FPGAs.

Main Methods:

• Developed a parallel BMME implementation in OpenCL for Intel Stratix 10 FPGAs.
• Synthesized and analyzed resource utilization on the target FPGA.
• Compared performance against optimized CPU implementations and a VHDL-based FPGA estimation.

Main Results:

• The OpenCL implementation efficiently processed Full HD frames entirely within the FPGA.
• Detailed resource utilization data for the Intel Stratix 10 FPGA was provided.
• Performance and resource utilization were benchmarked against CPU and VHDL alternatives.

Conclusions:

• OpenCL provides a viable and expressive high-level language for developing complex FPGA applications like motion estimation.
• The proposed OpenCL implementation demonstrates efficient processing capabilities for high-definition video on FPGAs.
• This work validates OpenCL as a practical alternative to traditional HDLs for FPGA-based video encoding acceleration.