A lightweight convolutional neural network hardware implementation for wearable heart rate anomaly detection.

Area of Science:

• Biomedical Engineering
• Computer Engineering
• Artificial Intelligence

Background:

• Existing wearable electrocardiogram (ECG) devices face limitations in accuracy and efficiency for detecting heart rhythm abnormalities.
• Deep neural networks (DNNs) offer potential for accurate classification but require significant computational resources, challenging for edge devices.
• Hardware acceleration is crucial for enabling real-time, low-power processing of complex algorithms on wearable health monitoring systems.

Purpose of the Study:

• To develop a lightweight and accurate heart rhythm abnormality classification model for ECG monitoring.
• To design a high-performance ECG rhythm abnormality monitoring coprocessor using deep neural networks and hardware acceleration.
• To address the shortcomings of current wearable ECG detection devices regarding efficiency and resource consumption.

Main Methods:

• Utilized classical convolutional neural networks (CNNs) within a deep neural network framework for heart rhythm classification.
• Implemented hardware acceleration techniques, including a 21-group floating-point multiplicative-additive computational array and an adder tree.
• Designed a chip using 16-bit floating-point inference for convolutional, pooling, and fully connected layers on a TSMC 65nm process.

Main Results:

• Achieved a high classification accuracy of 97.69% on the MIT-BIH arrhythmia database.
• Demonstrated a rapid classification time of 0.3 ms per heartbeat, enabling real-time analysis.
• The designed coprocessor exhibits a small area (0.191 mm²), low power consumption (1.1419 mW), and minimal storage requirement (5.12 kByte).

Conclusions:

• The proposed hardware architecture offers a compelling balance of high accuracy, simple structure, and low resource footprint for ECG monitoring.
• The coprocessor's efficiency and low power consumption make it suitable for deployment on edge devices with limited hardware capabilities.
• This approach significantly improves upon existing models in terms of data reuse, hardware implementation efficiency, and resource utilization.