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Calculating subtransient fault currents for three-phase faults in an N-bus power system involves using the positive-sequence network. When a three-phase short circuit occurs at a specific bus, the analysis uses the superposition method to evaluate two separate circuits.
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Biasing metal-semiconductor junctions involves applying a voltage across the junction. Specifically, the metal is connected to a voltage source, while the semiconductor is grounded. This technique is essential for controlling the direction and magnitude of current flow in electronic devices, including diodes, transistors, and photovoltaic cells.
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Biasing a Junction Field Effect Transistor (JFET) is crucial for setting operational parameters and ensuring efficient functioning in electronic circuits. JFETs are characterized by using a single carrier type in N-channel or P-channel configurations, where the channel is surrounded by PN junctions. These junctions are central to the device's ability to control current flow.
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Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
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Depletion-mode MOSFETs represent a unique subset of MOSFET technology, functioning fundamentally differently from their enhancement-mode counterparts. Unlike enhancement MOSFETs, which require a positive gate-source voltage (Vgs) to turn on, depletion-mode MOSFETs are inherently conductive and "normally on" devices.
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Machine Learning Algorithm for Efficient Design of Separated Buffer Super-Junction IGBT.

Ki Yeong Kim1, Tae Hyun Hwang1, Young Suh Song2

  • 1Department of Electrical Engineering, Pukyong National University, Busan 48513, Republic of Korea.

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|February 25, 2023
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Summary

This study introduces an improved Insulated Gate Bipolar Transistor (IGBT) structure with a separated buffer layer. Machine learning optimizes device parameters, significantly reducing simulation time and improving performance trade-offs.

Keywords:
breakdown voltage (BV)insulated gate bipolar transistor (IGBT)machine learning (ML)neural network (NN)on-state voltage (Von)optimizationpower semiconductorreverse engineeringsuper-junction IGBT (SJBT)trade-offturn-off loss (Eoff)

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Area of Science:

  • Semiconductor Device Physics
  • Power Electronics
  • Materials Science

Background:

  • Optimizing the trade-off between turn-off loss (E_off) and on-state voltage (V_on) in Insulated Gate Bipolar Transistors (IGBTs) is crucial for power electronics efficiency.
  • Conventional simulation methods face challenges with new design parameters, such as increased buffer doping concentration in separated buffer layer structures.

Purpose of the Study:

  • To present an improved IGBT structure with a separated buffer layer to enhance the E_off and V_on trade-off.
  • To propose and validate a machine learning (ML) algorithm for efficient parameter optimization and device analysis, overcoming limitations of traditional Technology Computer-Aided Design (TCAD) simulations.

Main Methods:

  • Implementation of a novel IGBT structure featuring a separated buffer layer.
  • Development and application of a machine learning algorithm for device parameter analysis and optimization.
  • Comparative analysis against conventional TCAD simulation tools to assess accuracy and speed.

Main Results:

  • The ML algorithm achieved high accuracy, with coefficients of determination (R^2) of 0.995 for V_on and 0.968 for E_off.
  • Optimizing the separated buffer concentration led to a 36.2% improvement in E_off, exceeding the ML-predicted 24.7% improvement.
  • The ML approach enabled inverse design, yielding four structures meeting target characteristics (E_off = 1.64 μJ, V_on = 1.38 V).

Conclusions:

  • The proposed separated buffer structure effectively improves the E_off and V_on trade-off in IGBTs.
  • Integrating ML into device analysis offers a strategic advantage for optimizing complex power electronic devices, reducing computational demands.
  • The ML-driven approach facilitates precise design, optimization, and reverse engineering of semiconductor devices.